Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput

Since the NULL Convention Logic (NCL) paradigm is delay-insensitive, NCL combinational circuits cannot be partitioned indiscriminately when pipelining, as can clocked circuits. Instead, these circuits must be partitioned into stages, such that each stage is inputcomplete with respect to all of its inputs and delayinsensitivity is maintained. Therefore the selected architecture for an NCL circuit may vary depending on whether or not the given circuit is to be pipelined. For example, the combinational circuit that has the shortest critical path may not necessarily result in optimal throughput when pipelined. This paper presents a method called Threshold Combinational Reduction for Pipelining (TCRP), to design NCL combinational circuits that will maximize throughput when pipelined. This method is demonstrated on the design of a 4-bit × 4-bit quad-rail multiplier and a dual-rail Booth2 multiplier, showing that both designs have an additional increased throughput after pipelining, when their combinational circuitry is designed using TCRP rather than the previous Threshold Combinational Reduction (TCR) method [1].